FPGA Hardware Design of Different LDPC Applications: Survey

Abstract

Low-Density Parity-Check (LDPC) error correction decoders emerge as a suitable path as long as offers a resilient error correction performance and its appropriateness to comparable hardware operation. This paper has been presented a case study to evaluate the use of LDPC code designs based on various features, such as flexibility, high processing speed, and the parallelism of Field-Programmable Gate Array (FPGA) devices. Hence, it has categorized the differences of key factors in FPGA-based LDPC decoder design and three crucial performance features are defined, such as processing throughput, processing latency, and hardware resource requirements. Furthermore, this word supports the concerned researchers to comprehend the differences between various related word and their results of most popular techniques.